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<title>CMSIS-Core (Cortex-A): Generic Interrupt Controller Functions</title>
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   &#160;<span id="projectnumber">Version 1.1.4</span>
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<a href="#nested-classes">Data Structures</a> &#124;
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<div class="title">Generic Interrupt Controller Functions<div class="ingroups"><a class="el" href="group__CMSIS__Core__FunctionInterface.html">Core Peripherals</a></div></div>  </div>
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<p>The Generic Interrupt Controller Functions grant access to the configuration, control and status registers of the Generic Interrupt Controller (GIC).  
<a href="#details">More...</a></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="nested-classes"></a>
Data Structures</h2></td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html">GICInterface_Type</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Structure type to access the Generic Interrupt Controller Interface (GICC)  <a href="structGICInterface__Type.html#details">More...</a><br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html">GICDistributor_Type</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Structure type to access the Generic Interrupt Controller Distributor (GICD)  <a href="structGICDistributor__Type.html#details">More...</a><br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:ga82e193c0016a9377274756b2673464a6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga82e193c0016a9377274756b2673464a6">GICDistributor</a>&#160;&#160;&#160;((<a class="el" href="structGICDistributor__Type.html">GICDistributor_Type</a>      *)     <a class="el" href="ARMCA9_8h.html#a5cc9c031f86d3fcb7efcbe2fce4cd552">GIC_DISTRIBUTOR_BASE</a> )</td></tr>
<tr class="memdesc:ga82e193c0016a9377274756b2673464a6"><td class="mdescLeft">&#160;</td><td class="mdescRight">GIC Distributor register set access pointer.  <a href="#ga82e193c0016a9377274756b2673464a6">More...</a><br/></td></tr>
<tr class="separator:ga82e193c0016a9377274756b2673464a6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga31a083dbdc5cb84178dbf184286180e3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga31a083dbdc5cb84178dbf184286180e3">GICInterface</a>&#160;&#160;&#160;((<a class="el" href="structGICInterface__Type.html">GICInterface_Type</a>        *)     <a class="el" href="ARMCA9_8h.html#adc560f42c09a0a3ce5dcc4aa898209ca">GIC_INTERFACE_BASE</a> )</td></tr>
<tr class="memdesc:ga31a083dbdc5cb84178dbf184286180e3"><td class="mdescLeft">&#160;</td><td class="mdescRight">GIC Interface register set access pointer.  <a href="#ga31a083dbdc5cb84178dbf184286180e3">More...</a><br/></td></tr>
<tr class="separator:ga31a083dbdc5cb84178dbf184286180e3"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:ga0f44df6823e90178183257e096e5cac6"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga0f44df6823e90178183257e096e5cac6">GIC_EnableDistributor</a> (void)</td></tr>
<tr class="memdesc:ga0f44df6823e90178183257e096e5cac6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable the interrupt distributor using the GIC's CTLR register.  <a href="#ga0f44df6823e90178183257e096e5cac6">More...</a><br/></td></tr>
<tr class="separator:ga0f44df6823e90178183257e096e5cac6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga363311538d4a4d750197b9936505d466"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga363311538d4a4d750197b9936505d466">GIC_DisableDistributor</a> (void)</td></tr>
<tr class="memdesc:ga363311538d4a4d750197b9936505d466"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable the interrupt distributor using the GIC's CTLR register.  <a href="#ga363311538d4a4d750197b9936505d466">More...</a><br/></td></tr>
<tr class="separator:ga363311538d4a4d750197b9936505d466"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7d93d39736ef5e379e6511430ee6e75f"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga7d93d39736ef5e379e6511430ee6e75f">GIC_DistributorInfo</a> (void)</td></tr>
<tr class="memdesc:ga7d93d39736ef5e379e6511430ee6e75f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read the GIC's TYPER register.  <a href="#ga7d93d39736ef5e379e6511430ee6e75f">More...</a><br/></td></tr>
<tr class="separator:ga7d93d39736ef5e379e6511430ee6e75f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1481d0cdf78f8c93fb2a710a519c4dc6"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga1481d0cdf78f8c93fb2a710a519c4dc6">GIC_DistributorImplementer</a> (void)</td></tr>
<tr class="memdesc:ga1481d0cdf78f8c93fb2a710a519c4dc6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reads the GIC's IIDR register.  <a href="#ga1481d0cdf78f8c93fb2a710a519c4dc6">More...</a><br/></td></tr>
<tr class="separator:ga1481d0cdf78f8c93fb2a710a519c4dc6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae86bba705d0d4ef812b84d29d7b3ca2b"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#gae86bba705d0d4ef812b84d29d7b3ca2b">GIC_SetTarget</a> (<a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn, uint32_t cpu_target)</td></tr>
<tr class="memdesc:gae86bba705d0d4ef812b84d29d7b3ca2b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sets the GIC's ITARGETSR register for the given interrupt.  <a href="#gae86bba705d0d4ef812b84d29d7b3ca2b">More...</a><br/></td></tr>
<tr class="separator:gae86bba705d0d4ef812b84d29d7b3ca2b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafccf881f9517592f30489bcabcb738a8"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#gafccf881f9517592f30489bcabcb738a8">GIC_GetTarget</a> (<a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
<tr class="memdesc:gafccf881f9517592f30489bcabcb738a8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read the GIC's ITARGETSR register.  <a href="#gafccf881f9517592f30489bcabcb738a8">More...</a><br/></td></tr>
<tr class="separator:gafccf881f9517592f30489bcabcb738a8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga758e5600d7f891e4f2f551bb45d07fce"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga758e5600d7f891e4f2f551bb45d07fce">GIC_EnableInterface</a> (void)</td></tr>
<tr class="memdesc:ga758e5600d7f891e4f2f551bb45d07fce"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable the CPU's interrupt interface.  <a href="#ga758e5600d7f891e4f2f551bb45d07fce">More...</a><br/></td></tr>
<tr class="separator:ga758e5600d7f891e4f2f551bb45d07fce"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0605877ad627c1f4320e518725fd103e"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga0605877ad627c1f4320e518725fd103e">GIC_DisableInterface</a> (void)</td></tr>
<tr class="memdesc:ga0605877ad627c1f4320e518725fd103e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable the CPU's interrupt interface.  <a href="#ga0605877ad627c1f4320e518725fd103e">More...</a><br/></td></tr>
<tr class="separator:ga0605877ad627c1f4320e518725fd103e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafc08bbc58b25fef0d24003313fd16eb8"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> <a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#gafc08bbc58b25fef0d24003313fd16eb8">GIC_AcknowledgePending</a> (void)</td></tr>
<tr class="memdesc:gafc08bbc58b25fef0d24003313fd16eb8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read the CPU's IAR register.  <a href="#gafc08bbc58b25fef0d24003313fd16eb8">More...</a><br/></td></tr>
<tr class="separator:gafc08bbc58b25fef0d24003313fd16eb8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac23f090f572a058b4a737f6613ded9cd"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#gac23f090f572a058b4a737f6613ded9cd">GIC_EndInterrupt</a> (<a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
<tr class="memdesc:gac23f090f572a058b4a737f6613ded9cd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Writes the given interrupt number to the CPU's EOIR register.  <a href="#gac23f090f572a058b4a737f6613ded9cd">More...</a><br/></td></tr>
<tr class="separator:gac23f090f572a058b4a737f6613ded9cd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaeba215d9c4ec3599e0a168800288c3f3"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#gaeba215d9c4ec3599e0a168800288c3f3">GIC_EnableIRQ</a> (<a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
<tr class="memdesc:gaeba215d9c4ec3599e0a168800288c3f3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enables the given interrupt using GIC's ISENABLER register.  <a href="#gaeba215d9c4ec3599e0a168800288c3f3">More...</a><br/></td></tr>
<tr class="separator:gaeba215d9c4ec3599e0a168800288c3f3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2102399d255690c0674209a6faeec13d"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga2102399d255690c0674209a6faeec13d">GIC_DisableIRQ</a> (<a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
<tr class="memdesc:ga2102399d255690c0674209a6faeec13d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disables the given interrupt using GIC's ICENABLER register.  <a href="#ga2102399d255690c0674209a6faeec13d">More...</a><br/></td></tr>
<tr class="separator:ga2102399d255690c0674209a6faeec13d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga18fbddf7f3594df141c97f61a71da47c"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga18fbddf7f3594df141c97f61a71da47c">GIC_SetPendingIRQ</a> (<a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
<tr class="memdesc:ga18fbddf7f3594df141c97f61a71da47c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sets the given interrupt as pending using GIC's ISPENDR register.  <a href="#ga18fbddf7f3594df141c97f61a71da47c">More...</a><br/></td></tr>
<tr class="separator:ga18fbddf7f3594df141c97f61a71da47c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5ad17ad70f23d1ff36015ffac33d383d"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga5ad17ad70f23d1ff36015ffac33d383d">GIC_ClearPendingIRQ</a> (<a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
<tr class="memdesc:ga5ad17ad70f23d1ff36015ffac33d383d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clears the given interrupt from being pending using GIC's ICPENDR register.  <a href="#ga5ad17ad70f23d1ff36015ffac33d383d">More...</a><br/></td></tr>
<tr class="separator:ga5ad17ad70f23d1ff36015ffac33d383d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga27b9862b58290276851ec669cabf0f71"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga27b9862b58290276851ec669cabf0f71">GIC_SetPriority</a> (<a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn, uint32_t priority)</td></tr>
<tr class="memdesc:ga27b9862b58290276851ec669cabf0f71"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the priority for the given interrupt in the GIC's IPRIORITYR register.  <a href="#ga27b9862b58290276851ec669cabf0f71">More...</a><br/></td></tr>
<tr class="separator:ga27b9862b58290276851ec669cabf0f71"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga397048004654f792649742f95bf8ae67"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga397048004654f792649742f95bf8ae67">GIC_GetPriority</a> (<a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
<tr class="memdesc:ga397048004654f792649742f95bf8ae67"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read the current interrupt priority from GIC's IPRIORITYR register.  <a href="#ga397048004654f792649742f95bf8ae67">More...</a><br/></td></tr>
<tr class="separator:ga397048004654f792649742f95bf8ae67"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa5eb0e76dbc89596e1ce47ddb9edc4a0"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#gaa5eb0e76dbc89596e1ce47ddb9edc4a0">GIC_SetInterfacePriorityMask</a> (uint32_t priority)</td></tr>
<tr class="memdesc:gaa5eb0e76dbc89596e1ce47ddb9edc4a0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the interrupt priority mask using CPU's PMR register.  <a href="#gaa5eb0e76dbc89596e1ce47ddb9edc4a0">More...</a><br/></td></tr>
<tr class="separator:gaa5eb0e76dbc89596e1ce47ddb9edc4a0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2c5f9e5637560fc9d5c29d772580a728"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga2c5f9e5637560fc9d5c29d772580a728">GIC_GetInterfacePriorityMask</a> (void)</td></tr>
<tr class="memdesc:ga2c5f9e5637560fc9d5c29d772580a728"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read the current interrupt priority mask from CPU's PMR register.  <a href="#ga2c5f9e5637560fc9d5c29d772580a728">More...</a><br/></td></tr>
<tr class="separator:ga2c5f9e5637560fc9d5c29d772580a728"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5dfedeb5403656a77e0fef4e1cc2c0c6"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga5dfedeb5403656a77e0fef4e1cc2c0c6">GIC_SetBinaryPoint</a> (uint32_t binary_point)</td></tr>
<tr class="memdesc:ga5dfedeb5403656a77e0fef4e1cc2c0c6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Configures the group priority and subpriority split point using CPU's BPR register.  <a href="#ga5dfedeb5403656a77e0fef4e1cc2c0c6">More...</a><br/></td></tr>
<tr class="separator:ga5dfedeb5403656a77e0fef4e1cc2c0c6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa7046d8206ddd4696716726e68f85906"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#gaa7046d8206ddd4696716726e68f85906">GIC_GetBinaryPoint</a> (void)</td></tr>
<tr class="memdesc:gaa7046d8206ddd4696716726e68f85906"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read the current group priority and subpriority split point from CPU's BPR register.  <a href="#gaa7046d8206ddd4696716726e68f85906">More...</a><br/></td></tr>
<tr class="separator:gaa7046d8206ddd4696716726e68f85906"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabc88483ecf94a2c222b644ecfa60eb9f"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#gabc88483ecf94a2c222b644ecfa60eb9f">GIC_GetIRQStatus</a> (<a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
<tr class="memdesc:gabc88483ecf94a2c222b644ecfa60eb9f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get the status for a given interrupt.  <a href="#gabc88483ecf94a2c222b644ecfa60eb9f">More...</a><br/></td></tr>
<tr class="separator:gabc88483ecf94a2c222b644ecfa60eb9f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2de8850780af26e802ee4cc43e9da6e9"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga2de8850780af26e802ee4cc43e9da6e9">GIC_SendSGI</a> (<a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn, uint32_t target_list, uint32_t filter_list)</td></tr>
<tr class="memdesc:ga2de8850780af26e802ee4cc43e9da6e9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Generate a software interrupt using GIC's SGIR register.  <a href="#ga2de8850780af26e802ee4cc43e9da6e9">More...</a><br/></td></tr>
<tr class="separator:ga2de8850780af26e802ee4cc43e9da6e9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8bb27e1bab132a8df44190adb996c2a1"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga8bb27e1bab132a8df44190adb996c2a1">GIC_GetHighPendingIRQ</a> (void)</td></tr>
<tr class="memdesc:ga8bb27e1bab132a8df44190adb996c2a1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get the interrupt number of the highest interrupt pending from CPU's HPPIR register.  <a href="#ga8bb27e1bab132a8df44190adb996c2a1">More...</a><br/></td></tr>
<tr class="separator:ga8bb27e1bab132a8df44190adb996c2a1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaba1b2665cdda47fc0bc3d7b90690dc50"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#gaba1b2665cdda47fc0bc3d7b90690dc50">GIC_GetInterfaceId</a> (void)</td></tr>
<tr class="memdesc:gaba1b2665cdda47fc0bc3d7b90690dc50"><td class="mdescLeft">&#160;</td><td class="mdescRight">Provides information about the implementer and revision of the CPU interface.  <a href="#gaba1b2665cdda47fc0bc3d7b90690dc50">More...</a><br/></td></tr>
<tr class="separator:gaba1b2665cdda47fc0bc3d7b90690dc50"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga07acd03d02683bb6e33e7f57f5f371d1"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga07acd03d02683bb6e33e7f57f5f371d1">GIC_DistInit</a> (void)</td></tr>
<tr class="memdesc:ga07acd03d02683bb6e33e7f57f5f371d1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Initialize the interrupt distributor.  <a href="#ga07acd03d02683bb6e33e7f57f5f371d1">More...</a><br/></td></tr>
<tr class="separator:ga07acd03d02683bb6e33e7f57f5f371d1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1c93f8af9f428cda8ec066bf4bfbade9"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga1c93f8af9f428cda8ec066bf4bfbade9">GIC_CPUInterfaceInit</a> (void)</td></tr>
<tr class="memdesc:ga1c93f8af9f428cda8ec066bf4bfbade9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Initialize the CPU's interrupt interface.  <a href="#ga1c93f8af9f428cda8ec066bf4bfbade9">More...</a><br/></td></tr>
<tr class="separator:ga1c93f8af9f428cda8ec066bf4bfbade9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga818881f69aae3eef6eb996bee6f6c63e"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga818881f69aae3eef6eb996bee6f6c63e">GIC_Enable</a> (void)</td></tr>
<tr class="memdesc:ga818881f69aae3eef6eb996bee6f6c63e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Initialize and enable the GIC.  <a href="#ga818881f69aae3eef6eb996bee6f6c63e">More...</a><br/></td></tr>
<tr class="separator:ga818881f69aae3eef6eb996bee6f6c63e"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<p>Reference: <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ihi0069c/index.html">Generic Interrupt Controller Architecture Specificaton</a>.</p>
<p>The following table shows the register naming of CMSIS in correlation with various technical reference manuals.</p>
<table class="doxtable">
<tr>
<th align="left">CMSIS Register Name </th><th align="left">Cortex-A5 TRM </th><th align="left">Cortex-A7 TRM </th><th align="left">Cortex-A9 TRM  </th></tr>
<tr>
<td align="left"><b>GIC Distributor</b> </td><td align="left"></td><td align="left"></td><td align="left"></td></tr>
<tr>
<td align="left"><a class="el" href="structGICDistributor__Type.html#a6ca67d9838ab3425864207c3a0399bd7">GICDistributor-&gt;CTLR</a> </td><td align="left">ICDDCR </td><td align="left">GICD_CTLR </td><td align="left">ICDDCR </td></tr>
<tr>
<td align="left"><a class="el" href="structGICDistributor__Type.html#a405823d97dc90dd9d397a3980e2cd207">GICDistributor-&gt;TYPER</a> </td><td align="left">ICDICTR </td><td align="left">GICD_TYPER </td><td align="left">ICDICTR </td></tr>
<tr>
<td align="left"><a class="el" href="structGICDistributor__Type.html#acebf65dae4cb82cd3c7deeefca9c9722">GICDistributor-&gt;IIDR</a> </td><td align="left">ICDIIDR </td><td align="left">GICD_IIDR </td><td align="left">ICDIIDR </td></tr>
<tr>
<td align="left"><a class="el" href="structGICDistributor__Type.html#ae24f260e27065660a2059803293084f2">GICDistributor-&gt;STATUSR</a> </td><td align="left"></td><td align="left"></td><td align="left"></td></tr>
<tr>
<td align="left"><a class="el" href="structGICDistributor__Type.html#afbdd372578e2cd6f998320282cc8ed25">GICDistributor-&gt;SETSPI_NSR</a> </td><td align="left"></td><td align="left"></td><td align="left"></td></tr>
<tr>
<td align="left"><a class="el" href="structGICDistributor__Type.html#a2f584d3fbeaa355faf234f2ee57d1168">GICDistributor-&gt;CLRSPI_NSR</a> </td><td align="left"></td><td align="left"></td><td align="left"></td></tr>
<tr>
<td align="left"><a class="el" href="structGICDistributor__Type.html#a6a9effdd633c6e75651d9f53caace306">GICDistributor-&gt;IGROUPR[]</a> </td><td align="left">ICDISR </td><td align="left">GICD_IGROUPRn </td><td align="left">ICDISRn </td></tr>
<tr>
<td align="left"><a class="el" href="structGICDistributor__Type.html#a1da3a2066b64644a0bb8a3066075ba87">GICDistributor-&gt;ISENABLER[]</a> </td><td align="left">ICDISER </td><td align="left">GICD_ISENABLERn </td><td align="left">ICDISERn </td></tr>
<tr>
<td align="left"><a class="el" href="structGICDistributor__Type.html#a390fa9f2f460951b2c6094932d890807">GICDistributor-&gt;ICENABLER[]</a> </td><td align="left">ICDICER </td><td align="left">GICD_ICENABLERn </td><td align="left">ICDICERn </td></tr>
<tr>
<td align="left"><a class="el" href="structGICDistributor__Type.html#a1c15cd75ce30d8946792e2a1a19556a5">GICDistributor-&gt;ISPENDR[]</a> </td><td align="left">ICDISPR </td><td align="left">GICD_ISPENDRn </td><td align="left">ICDISPRn </td></tr>
<tr>
<td align="left"><a class="el" href="structGICDistributor__Type.html#a0155cb4637845258e4ee76cd93cca2a6">GICDistributor-&gt;ICPENDR[]</a> </td><td align="left">ICDICPR </td><td align="left">GICD_ICPENDRn </td><td align="left">ICDICPRn </td></tr>
<tr>
<td align="left"><a class="el" href="structGICDistributor__Type.html#a5eb8e1ef5a88293e2759c41f6057ccc4">GICDistributor-&gt;ISACTIVER[]</a> </td><td align="left">ICDABR </td><td align="left">GICD_ISACTIVERn </td><td align="left">ICDABRn </td></tr>
<tr>
<td align="left"><a class="el" href="structGICDistributor__Type.html#ac0fd4c1ad19b5a332e403bb9966ba967">GICDistributor-&gt;ICACTIVER[]</a> </td><td align="left"></td><td align="left">GICD_ICACTIVERn </td><td align="left"></td></tr>
<tr>
<td align="left"><a class="el" href="structGICDistributor__Type.html#a08fa902293567e85dc6398dab58afaa9">GICDistributor-&gt;IPRIORITYR[]</a> </td><td align="left">ICDIPR </td><td align="left">GICD_IPRIORITYRn </td><td align="left">ICDIPRn </td></tr>
<tr>
<td align="left"><a class="el" href="structGICDistributor__Type.html#a6f1b07d48d3a9199f2effec8492f721c">GICDistributor-&gt;ITARGETSR[]</a> </td><td align="left">ICDIPTR </td><td align="left">GICD_ITARGETSRn </td><td align="left">ICDIPTRn </td></tr>
<tr>
<td align="left"><a class="el" href="structGICDistributor__Type.html#a9b306a630388c795d3cd32fc2e23a2b5">GICDistributor-&gt;ICFGR[]</a> </td><td align="left">ICDICFR </td><td align="left">GICD_ICFGRn </td><td align="left">ICDICFRn </td></tr>
<tr>
<td align="left"><a class="el" href="structGICDistributor__Type.html#ae9eeb19ca95d0b95828f1f98700b5689">GICDistributor-&gt;IGRPMODR[0]</a> </td><td align="left">ICDPPIS </td><td align="left">GICD_PPISR </td><td align="left">ppi_status </td></tr>
<tr>
<td align="left"><a class="el" href="structGICDistributor__Type.html#ae9eeb19ca95d0b95828f1f98700b5689">GICDistributor-&gt;IGRPMODR[31:1]</a> </td><td align="left">ICDSPIS </td><td align="left">GICD_SPISRn </td><td align="left">spi_status </td></tr>
<tr>
<td align="left"><a class="el" href="structGICDistributor__Type.html#a644abefb7064e434db20cc6dab5fe5f1">GICDistributor-&gt;NSACR[]</a> </td><td align="left"></td><td align="left"></td><td align="left"></td></tr>
<tr>
<td align="left"><a class="el" href="structGICDistributor__Type.html#a6ac65c4a5394926cc9518753a00d4da1">GICDistributor-&gt;SGIR</a> </td><td align="left">ICDSGIR </td><td align="left">GICD_SGIR </td><td align="left">ICDSGIR </td></tr>
<tr>
<td align="left"><a class="el" href="structGICDistributor__Type.html#a644a70cf4c12093c0277ce01f194b69b">GICDistributor-&gt;CPENDSGIR[]</a> </td><td align="left"></td><td align="left">GICD_CPENDSGIRn </td><td align="left"></td></tr>
<tr>
<td align="left"><a class="el" href="structGICDistributor__Type.html#ae40b4a50d9766c2bbf57441f68094f41">GICDistributor-&gt;SPENDSGIR[]</a> </td><td align="left"></td><td align="left">GICD_SPENDSGIRn </td><td align="left"></td></tr>
<tr>
<td align="left"><a class="el" href="structGICDistributor__Type.html#a73e0c679e5f45710deea474ab0d39cdb">GICDistributor-&gt;IROUTER[]</a> </td><td align="left"></td><td align="left"></td><td align="left"></td></tr>
<tr>
<td align="left"><b>GIC Interface</b> </td><td align="left"></td><td align="left"></td><td align="left"></td></tr>
<tr>
<td align="left"><a class="el" href="structGICInterface__Type.html#a5969edab40aa24e4d96e072af187a3a9">GICInterface-&gt;CTLR</a> </td><td align="left">ICPICR </td><td align="left">GICC_CTLR </td><td align="left">ICCICR </td></tr>
<tr>
<td align="left"><a class="el" href="structGICInterface__Type.html#a0edadabc6e3ce1f36d820f0b52bc143b">GICInterface-&gt;PMR</a> </td><td align="left">ICCIPMR </td><td align="left">GICC_PMRn </td><td align="left">ICCPMR </td></tr>
<tr>
<td align="left"><a class="el" href="structGICInterface__Type.html#a949317484547dc1db89c9f7ab40d1829">GICInterface-&gt;BPR</a> </td><td align="left">ICCBPR </td><td align="left">GICC_BPR </td><td align="left">ICCBPR </td></tr>
<tr>
<td align="left"><a class="el" href="structGICInterface__Type.html#aa48569605fc0c163e1db35321b4c76ea">GICInterface-&gt;IAR</a> </td><td align="left">ICCIAR </td><td align="left">GICC_IAR </td><td align="left">ICCIAR </td></tr>
<tr>
<td align="left"><a class="el" href="structGICInterface__Type.html#a4b9baa43aae026438bad64e63df17cdb">GICInterface-&gt;EOIR</a> </td><td align="left">ICCEOIR </td><td align="left">GICC_EOIR </td><td align="left">ICCEOIR </td></tr>
<tr>
<td align="left"><a class="el" href="structGICInterface__Type.html#a37762d42768ecb3d1302f34abc7f2821">GICInterface-&gt;RPR</a> </td><td align="left">ICCRPR </td><td align="left">GICC_RPR </td><td align="left">ICCRPR </td></tr>
<tr>
<td align="left"><a class="el" href="structGICInterface__Type.html#af793cd280a74bf73cca8c4fedfc329d6">GICInterface-&gt;HPPIR</a> </td><td align="left">ICCHPIR </td><td align="left">GICC_HPPIR </td><td align="left">ICCHPIR </td></tr>
<tr>
<td align="left"><a class="el" href="structGICInterface__Type.html#a6d3ca9eaae5e0ac38f20846a1e67180d">GICInterface-&gt;ABPR</a> </td><td align="left">ICCABPR </td><td align="left">GICC_ABPR </td><td align="left">ICCABPR </td></tr>
<tr>
<td align="left"><a class="el" href="structGICInterface__Type.html#a849e9ead6e9ced78dc6f0ba9256dd5a6">GICInterface-&gt;AIAR</a> </td><td align="left"></td><td align="left">GICC_AIAR </td><td align="left"></td></tr>
<tr>
<td align="left"><a class="el" href="structGICInterface__Type.html#a89d5a920c2b91b4b7bd0312ba4c38a89">GICInterface-&gt;AEOIR</a> </td><td align="left"></td><td align="left">GICC_AEOIR </td><td align="left"></td></tr>
<tr>
<td align="left"><a class="el" href="structGICInterface__Type.html#a12f25dec95ab3dd13a477573fab4b9c8">GICInterface-&gt;AHPPIR</a> </td><td align="left"></td><td align="left">GICC_AHPPIR </td><td align="left"></td></tr>
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<td align="left"><a class="el" href="structGICInterface__Type.html#abd978b408fb69b7887be2c422f48ce7e">GICInterface-&gt;STATUSR</a> </td><td align="left"></td><td align="left"></td><td align="left"></td></tr>
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<td align="left"><a class="el" href="structGICInterface__Type.html#aebae4bdcd3930372d639b85c5c9301e8">GICInterface-&gt;APR[]</a> </td><td align="left"></td><td align="left">GICC_APR0 </td><td align="left"></td></tr>
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<td align="left"><a class="el" href="structGICInterface__Type.html#ade3473ace2a8bf7c79a0251457be20f4">GICInterface-&gt;NSAPR[]</a> </td><td align="left"></td><td align="left">GICC_NSAPR0 </td><td align="left"></td></tr>
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<td align="left"><a class="el" href="structGICInterface__Type.html#aee78d0b6f64a7b47fbd730aabfcc86cf">GICInterface-&gt;IIDR</a> </td><td align="left">ICCIIDR </td><td align="left">GICC_IIDR </td><td align="left">ICCIDR </td></tr>
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<td align="left"><a class="el" href="structGICInterface__Type.html#a554bd1f88421df3189c664b9fd9c02aa">GICInterface-&gt;DIR</a> </td><td align="left"></td><td align="left">GICC_DIR </td><td align="left"></td></tr>
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<h2 class="groupheader">Macro Definition Documentation</h2>
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          <td class="memname">#define GICDistributor&#160;&#160;&#160;((<a class="el" href="structGICDistributor__Type.html">GICDistributor_Type</a>      *)     <a class="el" href="ARMCA9_8h.html#a5cc9c031f86d3fcb7efcbe2fce4cd552">GIC_DISTRIBUTOR_BASE</a> )</td>
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<p>Use GICDistributor to access the GIC Distributor registers.</p>
<p><b>Example:</b> </p>
<div class="fragment"><div class="line"><a class="code" href="group__GIC__functions.html#ga82e193c0016a9377274756b2673464a6">GICDistributor</a>-&gt;CTRL |= 1; <span class="comment">// Enable group 0 interrupts</span></div>
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          <td class="memname">#define GICInterface&#160;&#160;&#160;((<a class="el" href="structGICInterface__Type.html">GICInterface_Type</a>        *)     <a class="el" href="ARMCA9_8h.html#adc560f42c09a0a3ce5dcc4aa898209ca">GIC_INTERFACE_BASE</a> )</td>
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<p>Use GICInterface to access the GIC Interface registers.</p>
<p><b>Example:</b> </p>
<div class="fragment"><div class="line"><a class="code" href="group__GIC__functions.html#ga31a083dbdc5cb84178dbf184286180e3">GICInterface</a>-&gt;CTLR |= 1; <span class="comment">// Enable interrupt signaling</span></div>
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<h2 class="groupheader">Function Documentation</h2>
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          <td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> <a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> GIC_AcknowledgePending </td>
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<dl class="section return"><dt>Returns</dt><dd><a class="el" href="structGICInterface__Type.html#aa48569605fc0c163e1db35321b4c76ea" title="Offset: 0x00C (R/ ) Interrupt Acknowledge Register. ">GICInterface_Type::IAR</a></dd></dl>
<p>Provides the interrupt number of the highest priority interrupt pending. A read of this register acts as an acknowledge for the interrupt.</p>
<p>The read returns a spurious interrupt number of 1023 if any of the following apply:</p>
<ul>
<li>Forwarding of interrupts by the Distributor to the CPU interface is disabled.</li>
<li>Signaling of interrupts by the CPU interface to the connected PE is disabled.</li>
<li>There are no pending interrupts on the CPU interface with sufficient priority for the interface to signal it to the PE.</li>
</ul>
<dl class="section see"><dt>See Also</dt><dd><a class="el" href="group__GIC__functions.html#gac23f090f572a058b4a737f6613ded9cd" title="Writes the given interrupt number to the CPU&#39;s EOIR register. ">GIC_EndInterrupt</a> </dd></dl>

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          <td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void GIC_ClearPendingIRQ </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
          <td class="paramname"><em>IRQn</em></td><td>)</td>
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<dl class="params"><dt>Parameters</dt><dd>
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    <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>The interrupt to be enabled.</td></tr>
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<p>Removes the pending state from the corresponding interrupt. </p>

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          <td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void GIC_CPUInterfaceInit </td>
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<p>All software generated (SGIs) and private peripheral interrupts (PPIs) are initialized to be</p>
<ul>
<li>disabled</li>
<li>level-sensitive, 1-N model</li>
<li>priority 0x7F and the interrupt interface is enabled.</li>
</ul>
<p>The binary point is set to zero.</p>
<p>The interrupt priority mask is set to 0xFF.</p>
<dl class="section see"><dt>See Also</dt><dd><a class="el" href="group__GIC__functions.html#ga2102399d255690c0674209a6faeec13d" title="Disables the given interrupt using GIC&#39;s ICENABLER register. ">GIC_DisableIRQ</a><br/>
GIC_SetLevelModel<br/>
<a class="el" href="group__GIC__functions.html#ga27b9862b58290276851ec669cabf0f71" title="Set the priority for the given interrupt in the GIC&#39;s IPRIORITYR register. ">GIC_SetPriority</a><br/>
<a class="el" href="group__GIC__functions.html#ga758e5600d7f891e4f2f551bb45d07fce" title="Enable the CPU&#39;s interrupt interface. ">GIC_EnableInterface</a><br/>
<a class="el" href="group__GIC__functions.html#ga5dfedeb5403656a77e0fef4e1cc2c0c6" title="Configures the group priority and subpriority split point using CPU&#39;s BPR register. ">GIC_SetBinaryPoint</a><br/>
<a class="el" href="group__GIC__functions.html#gaa5eb0e76dbc89596e1ce47ddb9edc4a0" title="Set the interrupt priority mask using CPU&#39;s PMR register. ">GIC_SetInterfacePriorityMask</a><br/>
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          <td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void GIC_DisableDistributor </td>
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<p>Globally disable the forwarding of interrupts to the CPU interfaces. </p>
<dl class="section see"><dt>See Also</dt><dd><a class="el" href="group__GIC__functions.html#ga0f44df6823e90178183257e096e5cac6" title="Enable the interrupt distributor using the GIC&#39;s CTLR register. ">GIC_EnableDistributor</a> </dd></dl>

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          <td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void GIC_DisableInterface </td>
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<p>Resets the Enable bit in the local CPUs <a class="el" href="structGICInterface__Type.html#a5969edab40aa24e4d96e072af187a3a9">CTLR</a> register. Only the CPU executing the call is affected. </p>

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          <td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void GIC_DisableIRQ </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
          <td class="paramname"><em>IRQn</em></td><td>)</td>
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<dl class="params"><dt>Parameters</dt><dd>
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    <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>The interrupt to be disabled.</td></tr>
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<p>Disables forwarding of the corresponding interrupt to the CPU interfaces. </p>

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          <td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void GIC_DistInit </td>
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<p>All shared peripheral interrupts (SPIs) are initialized to be</p>
<ul>
<li>disabled</li>
<li>level-sensitive, 1-N model</li>
<li>priority 0x7F</li>
<li>targeting CPU0 and the distributor is enabled.</li>
</ul>
<dl class="section see"><dt>See Also</dt><dd><a class="el" href="group__GIC__functions.html#ga2102399d255690c0674209a6faeec13d" title="Disables the given interrupt using GIC&#39;s ICENABLER register. ">GIC_DisableIRQ</a><br/>
GIC_SetLevelModel<br/>
<a class="el" href="group__GIC__functions.html#ga27b9862b58290276851ec669cabf0f71" title="Set the priority for the given interrupt in the GIC&#39;s IPRIORITYR register. ">GIC_SetPriority</a><br/>
<a class="el" href="group__GIC__functions.html#gae86bba705d0d4ef812b84d29d7b3ca2b" title="Sets the GIC&#39;s ITARGETSR register for the given interrupt. ">GIC_SetTarget</a><br/>
<a class="el" href="group__GIC__functions.html#ga0f44df6823e90178183257e096e5cac6" title="Enable the interrupt distributor using the GIC&#39;s CTLR register. ">GIC_EnableDistributor</a> </dd></dl>

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          <td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t GIC_DistributorImplementer </td>
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          <td class="paramname"></td><td>)</td>
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<dl class="section return"><dt>Returns</dt><dd><a class="el" href="structGICDistributor__Type.html#acebf65dae4cb82cd3c7deeefca9c9722" title="Offset: 0x008 (R/ ) Distributor Implementer Identification Register. ">GICDistributor_Type::IIDR</a></dd></dl>
<p>Provides information about the implementer and revision of the Distributor. </p>

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          <td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t GIC_DistributorInfo </td>
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<dl class="section return"><dt>Returns</dt><dd><a class="el" href="structGICDistributor__Type.html#a405823d97dc90dd9d397a3980e2cd207" title="Offset: 0x004 (R/ ) Interrupt Controller Type Register. ">GICDistributor_Type::TYPER</a></dd></dl>
<p>Provides information about the configuration of the GIC. It indicates:</p>
<ul>
<li>whether the GIC implements the Security Extensions</li>
<li>the maximum number of interrupt IDs that the GIC supports</li>
<li>the number of CPU interfaces implemented</li>
<li>if the GIC implements the Security Extensions, the maximum number of implemented Lockable Shared Peripheral Interrupts (LSPIs). </li>
</ul>

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<p>Initializes the distributor and the cpu interface.</p>
<dl class="section see"><dt>See Also</dt><dd><a class="el" href="group__GIC__functions.html#ga07acd03d02683bb6e33e7f57f5f371d1" title="Initialize the interrupt distributor. ">GIC_DistInit</a> <a class="el" href="group__GIC__functions.html#ga1c93f8af9f428cda8ec066bf4bfbade9" title="Initialize the CPU&#39;s interrupt interface. ">GIC_CPUInterfaceInit</a> </dd></dl>

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<p>Globally enable the forwarding of interrupts to the CPU interfaces. </p>

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<p>Sets the Enable bit in the local CPUs <a class="el" href="structGICInterface__Type.html#a5969edab40aa24e4d96e072af187a3a9">CTLR</a> register. Only the CPU executing the call is affected. </p>

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          <td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void GIC_EnableIRQ </td>
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          <td class="paramtype"><a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
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<dl class="params"><dt>Parameters</dt><dd>
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<p>Enables forwarding of the corresponding interrupt to the CPU interfaces. </p>

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          <td class="paramtype"><a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
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<dl class="params"><dt>Parameters</dt><dd>
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<p>A write to this register performs priority drop for the specified interrupt.</p>
<p>For nested interrupts, the order of calls to this function must be the reverse of the order of interrupt acknowledgement, i.e. calls to <a class="el" href="group__GIC__functions.html#gafc08bbc58b25fef0d24003313fd16eb8">GIC_AcknowledgePending</a>. Behavior is UNPREDICTABLE if:</p>
<ul>
<li>This ordering constraint is not maintained.</li>
<li>The given interrupt number does not match an active interrupt, or the ID of a spurious interrupt.</li>
<li>The given interrupt number does not match the last valid interrupt value returned by <a class="el" href="group__GIC__functions.html#gafc08bbc58b25fef0d24003313fd16eb8">GIC_AcknowledgePending</a>. </li>
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<dl class="section return"><dt>Returns</dt><dd><a class="el" href="structGICInterface__Type.html#a949317484547dc1db89c9f7ab40d1829" title="Offset: 0x008 (R/W) Binary Point Register. ">GICInterface_Type::BPR</a></dd></dl>
<dl class="section see"><dt>See Also</dt><dd><a class="el" href="group__GIC__functions.html#ga5dfedeb5403656a77e0fef4e1cc2c0c6" title="Configures the group priority and subpriority split point using CPU&#39;s BPR register. ">GIC_SetBinaryPoint</a> </dd></dl>

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<dl class="section return"><dt>Returns</dt><dd><a class="el" href="structGICInterface__Type.html#af793cd280a74bf73cca8c4fedfc329d6" title="Offset: 0x018 (R/ ) Highest Priority Pending Interrupt Register. ">GICInterface_Type::HPPIR</a> </dd></dl>

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<dl class="section return"><dt>Returns</dt><dd><a class="el" href="structGICInterface__Type.html#aee78d0b6f64a7b47fbd730aabfcc86cf" title="Offset: 0x0FC (R/ ) CPU Interface Identification Register. ">GICInterface_Type::IIDR</a> </dd></dl>

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          <td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t GIC_GetInterfacePriorityMask </td>
          <td>(</td>
          <td class="paramtype">void&#160;</td>
          <td class="paramname"></td><td>)</td>
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<dl class="section return"><dt>Returns</dt><dd><a class="el" href="structGICInterface__Type.html#a0edadabc6e3ce1f36d820f0b52bc143b" title="Offset: 0x004 (R/W) Interrupt Priority Mask Register. ">GICInterface_Type::PMR</a></dd></dl>
<dl class="section see"><dt>See Also</dt><dd><a class="el" href="group__GIC__functions.html#gaa5eb0e76dbc89596e1ce47ddb9edc4a0" title="Set the interrupt priority mask using CPU&#39;s PMR register. ">GIC_SetInterfacePriorityMask</a> </dd></dl>

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          <td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t GIC_GetIRQStatus </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
          <td class="paramname"><em>IRQn</em></td><td>)</td>
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<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>The interrupt to get status for. </td></tr>
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<dl class="section return"><dt>Returns</dt><dd>0 - not pending/active, 1 - pending, 2 - active, 3 - pending and active</dd></dl>
<p>The return value is a combination of GIC's <a class="el" href="structGICDistributor__Type.html#a5eb8e1ef5a88293e2759c41f6057ccc4">ISACTIVER</a> and <a class="el" href="structGICDistributor__Type.html#a1c15cd75ce30d8946792e2a1a19556a5">ISPENDR</a> registers.</p>
<p>Bit 0 denotes interrupts pending bit (interrupt should be handled) and bit 1 denotes interrupts active bit (interrupt is currently handled). </p>

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          <td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t GIC_GetPriority </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
          <td class="paramname"><em>IRQn</em></td><td>)</td>
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<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>The interrupt to be queried.</td></tr>
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<p>Can be used to retrieve the actual priority depending on the GIC implementation. </p>
<dl class="section see"><dt>See Also</dt><dd><a class="el" href="group__GIC__functions.html#ga27b9862b58290276851ec669cabf0f71" title="Set the priority for the given interrupt in the GIC&#39;s IPRIORITYR register. ">GIC_SetPriority</a> </dd></dl>

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          <td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t GIC_GetTarget </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
          <td class="paramname"><em>IRQn</em></td><td>)</td>
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<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Interrupt to acquire the configuration for. </td></tr>
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<dl class="section return"><dt>Returns</dt><dd><a class="el" href="structGICDistributor__Type.html#a6f1b07d48d3a9199f2effec8492f721c" title="Offset: 0x800 (R/W) Interrupt Targets Registers. ">GICDistributor_Type::ITARGETSR</a></dd></dl>
<p>Read the current interrupt to CPU assignment for the given interrupt. </p>
<dl class="section see"><dt>See Also</dt><dd><a class="el" href="group__GIC__functions.html#gae86bba705d0d4ef812b84d29d7b3ca2b" title="Sets the GIC&#39;s ITARGETSR register for the given interrupt. ">GIC_SetTarget</a> </dd></dl>

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          <td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void GIC_SendSGI </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
          <td class="paramname"><em>IRQn</em>, </td>
        </tr>
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          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>target_list</em>, </td>
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          <td class="paramkey"></td>
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          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>filter_list</em>&#160;</td>
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          <td></td>
          <td>)</td>
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<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Software interrupt to be generated. </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">target_list</td><td>List of CPUs the software interrupt should be forwarded to. </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">filter_list</td><td>Filter to be applied to determine interrupt receivers. </td></tr>
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          <td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void GIC_SetBinaryPoint </td>
          <td>(</td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>binary_point</em></td><td>)</td>
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<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">binary_point</td><td>Amount of bits used as subpriority.</td></tr>
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<p>The binary point defines the amount of priority bits used as a group priority and subpriorities.</p>
<p>Interrupts sharing the same group priority do not preempt each other. But interrupts having a higher group priority (lower value) preempt interrups with a lower group priority.</p>
<p>The subpriority defines the execution sequence of interrupts with the same group priority if multiple are pending at time. </p>

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          <td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void GIC_SetInterfacePriorityMask </td>
          <td>(</td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>priority</em></td><td>)</td>
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<dl class="params"><dt>Parameters</dt><dd>
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    <tr><td class="paramdir">[in]</td><td class="paramname">priority</td><td>Priority mask to be set.</td></tr>
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<p>Only interrupts with a higher priority (lower values) than the value provided are signaled. </p>

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          <td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void GIC_SetPendingIRQ </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
          <td class="paramname"><em>IRQn</em></td><td>)</td>
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<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>The interrupt to be enabled.</td></tr>
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<p>Adds the pending state to the corresponding interrupt. </p>

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          <td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void GIC_SetPriority </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
          <td class="paramname"><em>IRQn</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>priority</em>&#160;</td>
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          <td></td>
          <td>)</td>
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<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>The interrupt to be configured. </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">priority</td><td>The priority for the interrupt, lower values denote higher priorities.</td></tr>
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<p>Configures the priority of the given interrupt.</p>
<p>The available interrupt priorities are IMPLEMENTATION DEFINED. In order to query the actual priorities one can</p>
<div class="fragment"><div class="line"><a class="code" href="group__GIC__functions.html#ga27b9862b58290276851ec669cabf0f71">GIC_SetPriority</a>(IRQn_TIM1, UINT32_MAX);       <span class="comment">// try to configure lowest possible priority</span></div>
<div class="line">uint32_t actual = <a class="code" href="group__GIC__functions.html#ga397048004654f792649742f95bf8ae67">GIC_GetPriority</a>(IRQn_TIM1); <span class="comment">// retrieve actual lowest priority usable</span></div>
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          <td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void GIC_SetTarget </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
          <td class="paramname"><em>IRQn</em>, </td>
        </tr>
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          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>cpu_target</em>&#160;</td>
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          <td>)</td>
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<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Interrupt to be configured. </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">cpu_target</td><td>CPU interfaces to assign this interrupt to.</td></tr>
  </table>
  </dd>
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<p>The <a class="el" href="structGICDistributor__Type.html#a6f1b07d48d3a9199f2effec8492f721c">ITARGETSR</a> registers provide an 8-bit CPU targets field for each interrupt supported by the GIC. This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. </p>

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